1. Field of the Invention
This invention relates to a method of design analysis of existing integrated circuits, and more particularly to the determination of the location of standard cells in an image of an IC layout.
2. Background Art
In the intensely competitive field of microelectronics, detailed analysis of a semiconductor integrated circuit product can provide valuable information as to how a particular technical problem was dealt with, overall strengths and weaknesses of a design approach, and the like. This information can be used to make decisions regarding market positioning, future designs and new product development. The information resulting from analysis of the product is typically provided through circuit extraction (reverse engineering), functional analysis and other technical means. At the core of this activity is the process of design analysis, which, in this context, refers to the techniques and methodology of deriving complete or partial schematics, starting with essentially any type of integrated circuit in any process technology. For such technical information to be of strategic value, it must be accurate and cost-effective, and it is very important that the information should be timely.
A design analysis process typically involved skilled engineers manually extracting circuit information from a set of large “photomosaics” of an integrated circuit (IC). Photomosaics are high magnification photographs of portions of an IC mosaicked or stitched together. To properly extract the circuitry, photomosaics of each polysilicon (poly) and metal layer are required. Due to advances in image processing and electron microscopy, photomosaics have been replaced with computer workstations. Topographical images of the die can be viewed on a computer through dedicated software. Each metal layer is shown as a different colour to differentiate between each other. The layers can be selected and de-selected so the engineer can view selected layers instead of all of them. Although this technique is less time-consuming than the use of photomosaics, the engineer must still manually extract all the circuitry. What is especially time-consuming is the extraction of standard cells. Standard cells can make up a large part of an IC, yet the engineer must manually extract each standard cell individually.
In order to create an efficient automated system for extracting standard cells, there are several issues that need to be addressed:                A. The poly layer of each standard cell instance is usually identical, but some of the lower metal layers can be changed from one instance to another.        B. The gray-scale image of every poly and metal layer is at least several gigabytes in size.        C. The layers are not usually perfectly aligned with one another. It is possible that the layers can be misaligned by a few pixels.        D. The poly layers typically have low contrast, high noise and contain visible distortions and brightness/contrast variations.        E. The layers typically contain many thin lines (about 3-4 pixels), so the automated standard cell extraction system must be sensitive enough to account for these lines.        F. The images can contain other cells that are very similar. The difference may be only in a couple of low contrast lines.        
In order to overcome the above-described manual process, automated systems have been designed. Such systems are described in U.S. Pat. No. 5,086,477, which issued to Yu et al on Feb. 4, 1992 and U.S. Pat. No. 5,191,213, which issued to Ahmed et al on Mar. 2, 1993.
In the system described in U.S. Pat. No. 5,086,477—Yu et al, the integrated circuit chip is scanned by a microscope or scanning electron microscope (SEM). The system identifies every unique cell and/or gate used in the integrated circuit. A unique abstract representation is created for each of these unique cells or gates, which are stored in a library.
In this patented system, once all unique cells have been captured in a reference library, the system attempts to associate and match all abstract features contained in the layout database to the cells in the reference library using classical template matching. However because of the magnitude of data contained in a layout database for a typical modern integrated circuit, even after the data has been compressed, the processing time required to reliably extract a netlist is excessive, and Yu et al therefore teaches that the tasks should be (manually) operator directed. The difficulty and time required for the operator directed process increases with a larger number of cells or gates, since the number of template matching operations augments exponentially with the number of reference cells and/or gates.
Once all reference cells in the Yu et al system have been template matched to the database, theoretically all features in the layout database will have been grouped and classified and a netlist can be constructed. If there are features of the layout database that have not been classified, either the system must construct a new cell or gate to be added to the reference library and an operator is informed, or the operator is informed by the system and the operator performs this task. The cell to cell interconnects information extraction, which is required to construct a netlist, is said to be performed using template matching, which is very inefficient.
Due to the template matching approach that is required, the Yu et al system must be limited to gate-array or very structured standard cell integrated circuit analysis in which the large majority of the cells are identical, and therefore as the size of the integrated circuits increases, its efficiency decreases. It is therefore inefficient for analysis of modern ASICs or custom integrated circuits, large and/or complex integrated circuits. The Yu et al system would also be limited to applications where many devices from a few ASIC manufacturers are investigated, due to the investment and time required to develop separate reference libraries, e.g. related to a different set of design rules.
U.S. Pat. No. 5,191,213—Ahmed et al relates to a technique for removing layers of an integrated circuit and for scanning each of the layers, and does not appear to be an automated system.
The paper: L. R. Avery, J. S. Crabbe, S. Al Sofi, H. Ahmed, J. R. A. Cleaver and D. J. Weaver “Reverse engineering complex application-specific integrated circuits (ASICs)” DMSMS Conference 2002, discloses an automated macro (standard cell) extraction method where via and contact information are used to find probable locations of macros. In some cases, contact information is not readily available due to imaging and/or sample preparation issues. In other cases, such as gate arrays, contact patterns are very repetitive and cannot be used for finding even a preliminary location.
An example of an object localization method that uses point of interest matching and descriptors to characterize the vicinity of the point of interest is disclosed in U.S. Pat. No. 6,711,293, which issued to Lowe on Mar. 23, 2004. This method uses some statistics of histograms in vicinities of points of interest. The points of interest used in this method are pixel amplitude extremes.
All of the above references are herein incorporated by reference.
Therefore, there is a need for a computationally affordable template matching method for finding standard cells in reverse engineered multi-layer images of an IC layout.